1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device and an operating method thereof capable of performing several operations by receiving clock signals and data signals.
2. Description of the Related Art
Generally, a semiconductor memory device including a double data rate synchronous DRAM (DDR SDRM) receives clock signals and data signals from an external controller to perform operations such as reading and writing, or the like. In this case, the external controller transfers the clock signals and the data signals together with strobe signals used to synchronize the clock signals and the data signals. However, the method may cause a skew between the clock signals and the data signals and suffer various types of external noises, so that it may be difficult to secure a stable operation of the semiconductor memory device. Therefore, a clock data recovery method has been recently used.
The clock data recovery method includes recovering the clock signals from the data signals and thus, the external controller does not transfer the separate data strobe signals. Therefore, the clock data recovery method may not include a configuration for transferring the data strobe signals required in the related art and may not consider various types of noises reflected in the data strobe signals.
However, in order to secure a margin in which the clock signals and the data signals are synchronized with each other, the clock data recovery method may require a delay circuit for simply delaying the clock signals or the data signals by a given time within the circuit and reflect the undesired noises to the clock signals and the data signals due to the delay configuration.